Design a small Sound card for Next

Everything that is not ZX Spectrum Next goes here. Get ready for the Nostalgia!
PiyoTaro
Posts: 181
Joined: Thu Jun 01, 2017 11:13 am

Re: Design a small Sound card for Next

Post by PiyoTaro » Thu May 23, 2019 5:01 pm

Let's discuss "connectors and cases" first after my prototype works, and then investigate how many people want them as products.

First of all my prototype is not working.
It is necessary to verify why the decoder circuit was designed by "my misunderstanding" or whether the implementation of the extension port of ZX Spectrum Next is incomplete.
seedy1812 wrote:
Thu May 23, 2019 4:44 pm
If you read the description it seems the Speccy edge connectors come from a bigger / longer item and they cut them to size and block one of the pins. If you did that all yourself then costs would come down.

For prototyping https://www.tindie.com/products/TRC/zx- ... rd-adapter would be ideal ( $8 + $14 shipping to the uk ) (only 2 left ). Should be only 1 shipping cost even if you get 10 edge connectors
PiyoTaro wrote:
Thu May 23, 2019 1:30 pm
seedy1812 wrote:
Thu May 23, 2019 10:20 am
Have you seen https://www.tindie.com/products/TRC/zx- ... connector/ $2.25 when 10+ units ordered

Back in the day companies were producing different expansion add ons. Some were plain through connectors either fixed or with a cable and I had one where was like a T junction so you had a vertical and horsizontal edge connector so you could plug 2 items in.
Thank you for the advice.
(The connector is $2.75 a piece, but it seems to cost $14 shipping to me.)
How about putting the module designed by "pin socket" on the conversion board connected to "edge connector"? Design a "cartridge type case or dust cover" that houses the module on the conversion board.


I am studying EAGLE at the same time as prototyping.
If I would like to distribute the board as a "Speecy expansion device", I thought that the OPN3 with more functions (3ch SSG,6ch Drums like YM2608. In the FM chip, it's probably a new product launched after 2000) than the OPN2 would be better, and I designed a smaller and half-sized module.

But unfortunately my prototype didn't work. I will post a verification article later.

PiyoTaro
Posts: 181
Joined: Thu Jun 01, 2017 11:13 am

Re: Design a small Sound card for Next

Post by PiyoTaro » Thu May 23, 2019 5:22 pm

PiyoTaro wrote:
Tue Apr 30, 2019 1:52 pm
PiyoTaro wrote:
Sat Apr 20, 2019 6:30 pm
PiyoTaro wrote:
Fri Apr 12, 2019 7:25 pm
This project aims at a small FM sound card that can be put on the pin header terminal CN5 (on the ZX Spectrum Next board).
Prototype the FM sound module.
---

I mounted the components on the board at last weekend. Compare with the layout
(Postscript. The wiring could not be shown because only 3 photos can be attached).
I have not yet wired the busline. The schematic will be posted in the next post.

Image
The module did not work at the last post.

First, the amplifier oscillated and made a intermittent noise.

I tried to use "-5V" as the op-amp power supply, but no voltage was output to the expansion port.
This is because I can not judge whether this is "an incomplete implementation of the expansion port" or a specification of the "+3/128" edge connector, so I have posted a question on the forum.
There is no answer to my question yet.
PiyoTaro wrote:
Sat May 04, 2019 9:12 am
Are there any voltages other than 5V at the edge connector?

Please tell me whether the voltage of "minus 5 volts" is supplied to "pin 39" of header CN5.

viewtopic.php?f=9&t=1365
Image


The original "MegaAmp" uses a resistor to divide 5V and uses 2.9V as a reference voltage. I modified this circuit.
(Photo. May 4)
20190523_busline20190504_20190430final_proto.jpg
20190523_busline20190504_20190430final_proto.jpg (290.62 KiB) Viewed 759 times

But, a high frequency noise was generated that was so large as to offset the music on the motherboard.

---
I was disappointed, so I decided to manufacture a printed circuit board.

The "discount campaign" maker (described above) did not indicate the "delivery date". I tried adding an "express charge". However, my order was not processed correctly and the air bag arrived seven days later.
My "layout diagram" drawn in 2.54mm increments without understanding the "layer" was manufactured as a double-sided printed circuit board. The cost is $19.
(Photo. May 17)
20190523_20190517mypcb.jpg
20190523_20190517mypcb.jpg (266.79 KiB) Viewed 759 times

(The article continues)

PiyoTaro
Posts: 181
Joined: Thu Jun 01, 2017 11:13 am

Do not work!/Re: Design a small Sound card for Next

Post by PiyoTaro » Thu May 23, 2019 5:31 pm

PiyoTaro wrote:
Thu May 23, 2019 5:22 pm
PiyoTaro wrote:
Tue Apr 30, 2019 1:52 pm
PiyoTaro wrote:
Sat Apr 20, 2019 6:30 pm
My "layout diagram" drawn in 2.54mm increments without understanding the "layer" was manufactured as a double-sided printed circuit board. The cost is $19.(Photo. May 17)

(The article continues)
PCB board module does not work
(Photo. May 17)
20190523_20190517mypcb_top.jpg
20190523_20190517mypcb_top.jpg (211.21 KiB) Viewed 756 times
20190523_20190517mypcb_bottom.jpg
20190523_20190517mypcb_bottom.jpg (248.84 KiB) Viewed 758 times
  • Were there any problems with the software I wrote in Boriel BASIC?

    Because "hexadecimal" can not be handled in ZX BASIC, I tried using the Boriel compiler somehow. (However, in order to use ZXSpectrumNext in "ZXSpectrum 48K and other ZX compatible machine modes", I realized later that software for operating the SD card drive is required separately)
    • Does the "OUT" statement correspond to a 16-bit IO address?

      --> I wrote and verified a demo program to control TSNext's AY register.

  • Is there a problem with the module design, "address decoder circuit"?
    20190523_20190510timexfm_schematic.png
    20190523_20190510timexfm_schematic.png (31.43 KiB) Viewed 758 times
    First, I checked whether the output pin of HC138 is usually H level.

    The four signals of A4-A7 are connected to HC08, the output of HC08 and five signals of A0-A3 and /IORQ are connected to HC138.
    Even before bringing out the logic analyzer, I would like to confirm the trigger with the oscilloscope on the weekend.

---

Image


  • By the way, is the signal coming to the edge connector of ZXSpectrumNext?

    I was posting a quote for the FB article in another thread. I was interpreting that "the edge connector does not work in turbo mode faster than 3.5MHz clock".

    Does not "Next mode" mean to boot as "ZX Spectrum Next" by boot ROM selection?

    There is no answer to my question yet.
    PiyoTaro wrote:
    Wed May 22, 2019 11:02 am
    About the Legacy Machine mode.
    Please tell me how to make NMI/SD card drive work with Legacy 48K/128K ROM system.

    Does the current version of "TBBlue SD Distribution" not include software that supports "DivMMC"?

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Timbucus
Posts: 230
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Re: Design a small Sound card for Next

Post by Timbucus » Mon May 27, 2019 5:10 pm

I am no expert but, as you say you will need to be in 48k or 128k mode and disable any conflicting devices. Definitely do not run above 3.5Mhz for the expansion BUS to work - later versions of the system will likely disable it at higher speeds anyway. I think you have already found that the -5v signal is not present as the board only generates from the 9V - 5, 3.3 and 1.2, neither is the YUV but, that should not affect this use case. Although the schematic shows the line that is only the name - you can see the -5V is not generated internally on the PSU part of the Schematic:

https://gitlab.com/thesmog358/tbblue/bl ... ecNext.PDF
I'm Infinite Imaginations when not in work... PAWS for thought.

Alcoholics Anonymous
Posts: 513
Joined: Mon May 29, 2017 7:00 pm

Re: Do not work!/Re: Design a small Sound card for Next

Post by Alcoholics Anonymous » Mon May 27, 2019 6:22 pm

PiyoTaro wrote:
Thu May 23, 2019 5:31 pm
Is there a problem with the module design, "address decoder circuit"?
It looks like your interface responds to port 0xf5 and 0xf6. Do you actually need two ports? It looks like you only need one as both are being used as /cs for the ic. If this is intended to operate in cooperation with the timex wiring of the ay chip then I think it's $f5 to read/write the register selection and $f6 to read/write the register data. But this is from memory so check if you don't already know.

If you check at the bottom of this page:

https://www.specnext.com/tbblue-io-port-system/

you will see the current port io decoding.

The ula in the original spectrums responds to all even ports, including 0xf6 so you have a conflict there.
0xf5 is conflicting with all the xxFD ports.

If the /IORQULA signal is available (and it is on the next) then forcing this high when your part decides to respond will disable port 0xfe inside the spectrum to remove the conflict with 0xf6. This disabling is not currently done for the xxFD ports but likely will be.

That's the current public core.

On the development core, /IORQULA (sometimes called /IORQGE; on the timex machines I'm not sure if it's there and I'm not sure it's needed as everything is fully decoded on a timex) needs to be asserted very early, ahead of /IORQ using the address lines only. The reason is the next is going to be filtering io cycles from the expansion bus if an internal device responds. So if you want to stop, eg, 0xfe responding internally when io to port 0xf6 is occurring, then the /IORQULA signal has to be stable before /IORQ goes low. In your design, you're decoding ports 0xf5 and 0xf6 using the /IORQ signal in the equation.

So long story short, you have port conflicts in your current design.
I was posting a quote for the FB article in another thread. I was interpreting that "the edge connector does not work in turbo mode faster than 3.5MHz clock".
Does not "Next mode" mean to boot as "ZX Spectrum Next" by boot ROM selection?
There is no answer to my question yet.
The expansion bus is being developed right now. In the current public core there are no controls. If you run faster than 3.5MHz, the expansion bus will be running faster than 3.5MHz. If booting into NextZXOS, NextZXOS itself will be speeding up and slowing down as it runs its tasks. In the personalities, as a 48k / 128k, the machine will be running at a constant speed set by nextreg 0x07 which will be 3.5MHz by default.

The development core will be solving all the issues with port conflicts and compatibility with legacy peripherals.
PiyoTaro wrote:
Wed May 22, 2019 11:02 am
About the Legacy Machine mode.
Please tell me how to make NMI/SD card drive work with Legacy 48K/128K ROM system.
Does the current version of "TBBlue SD Distribution" not include software that supports "DivMMC"?
I think it was mentioned already, you'll need to install esxdos for the 48k/128k/pentagon personalities so they have access to the sd card. Otherwise you will have a plain tape-based machine. The config file also has to be updated to indicate to the boot sequence that you are enabling esxdos.

PiyoTaro
Posts: 181
Joined: Thu Jun 01, 2017 11:13 am

Re: Design a small Sound card for Next

Post by PiyoTaro » Mon May 27, 2019 6:28 pm

Timbucus wrote:
Mon May 27, 2019 5:10 pm
I am no expert but, as you say you will need to be in 48k or 128k mode and disable any conflicting devices. Definitely do not run above 3.5Mhz for the expansion BUS to work - later versions of the system will likely disable it at higher speeds anyway. I think you have already found that the -5v signal is not present as the board only generates from the 9V - 5, 3.3 and 1.2, neither is the YUV but, that should not affect this use case. Although the schematic shows the line that is only the name - you can see the -5V is not generated internally on the PSU part of the Schematic:

https://gitlab.com/thesmog358/tbblue/bl ... ecNext.PDF
As the signal name was added to the drawing of the connector on the official wiki, I thought that there was a power reversal circuit. The FPGA can create analog circuits internally.

Also, I did not notice this time because the clock oscillator was mounted on the board, but is the signal coming to "CPU CLK 3.5"?

I do not have to order a printed circuit board for prototyping, buy a tiny logic analyzer, or do not have to.

---
In fact, I saw a test program of "ZX-HD" at YouTube, which was written in his recent blog, but is "edge connector" properly implemented in the first place?

YouTube:
The ByteDelight Weekly Show #23 - 19 January 2019 https://www.youtube.com/watch?v=OpEIWoOuFE4&t=4032

Blog:
"MY THOUGHTS ON FPGA BASED ZX SPECTRUM CLONES" Posted on 14 May 2019 by bverstee https://www.bytedelight.com/?p=4762

PiyoTaro
Posts: 181
Joined: Thu Jun 01, 2017 11:13 am

Re: Design a small Sound card for Next

Post by PiyoTaro » Mon May 27, 2019 7:06 pm

Hmmm. I will search the literature for "/IORQULA". :shock:

I was told that this is a function after "ZX Spectrum +2".

---
Solution:

If there is a conflicting problem in decoding the "even" address, will the problem not occur if "A0" is not used?
“A0” is connected to the sound chip “A0”.
In addition to the 8-bit IO decoding, A8 and A9 are used for TIMEX's AY interface that I referred to.

I will try prototyping using "A9" instead of "A0".
  • Z80 I/O address:"%xxxx xxNN 1111 01Nx"(F5 is also F4 ; F7 is also F6)

    $02F5: OPN2 bank 0 address
    $00F7: OPN2 bank 0 data
    $03F5: OPN2 bank 1 address
    $01F7: OPN2 bank 1 data
'$F7' Conflicts; Interface 1 RS232/Network Data
(Maybe I will make a circuit that decodes only '$F5'.)

Alcoholics Anonymous wrote:
Mon May 27, 2019 6:22 pm
PiyoTaro wrote:
Thu May 23, 2019 5:31 pm
Is there a problem with the module design, "address decoder circuit"?
The ula in the original spectrums responds to all even ports, including 0xf6 so you have a conflict there.
0xf5 is conflicting with all the xxFD ports.

If the /IORQULA signal is available (and it is on the next) then forcing this high when your part decides to respond will disable port 0xfe inside the spectrum to remove the conflict with 0xf6. This disabling is not currently done for the xxFD ports but likely will be.

That's the current public core.

On the development core, /IORQULA (sometimes called /IORQGE; on the timex machines I'm not sure if it's there and I'm not sure it's needed as everything is fully decoded on a timex) needs to be asserted very early, ahead of /IORQ using the address lines only. The reason is the next is going to be filtering io cycles from the expansion bus if an internal device responds. So if you want to stop, eg, 0xfe responding internally when io to port 0xf6 is occurring, then the /IORQULA signal has to be stable before /IORQ goes low. In your design, you're decoding ports 0xf5 and 0xf6 using the /IORQ signal in the equation.

So long story short, you have port conflicts in your current design.

Alcoholics Anonymous
Posts: 513
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Re: Design a small Sound card for Next

Post by Alcoholics Anonymous » Mon May 27, 2019 8:20 pm

PiyoTaro wrote:
Mon May 27, 2019 6:28 pm
Also, I did not notice this time because the clock oscillator was mounted on the board, but is the signal coming to "CPU CLK 3.5"?
Yes. The cpu clock is generated inside the fpga and is routed to the expansion bus from there. It's commonly labelled /clock (clock inverted) but it corresponds to waveforms seen in the zilog manuals.
In fact, I saw a test program of "ZX-HD" at YouTube, which was written in his recent blog, but is "edge connector" properly implemented in the first place?
There are several issues with his device. He snoops the bus to decide what model the spectrum is (I'm not sure how) but the next has a 2-stage boot process which begins as a 48k machine and ends as whatever model was selected. So he needs to delay determining the model some time later on.

I don't know how his device works. If it's relying on YUV signals, they aren't there. If it's watching for memory writes to the display area, they are there but his device will only display the standard ula screens and not the rest of the next's display layers. So at most it's a partial solution.

But really I don't know what the interface needs to know if there is a problem. Maybe another go after the development core deals with the expansion bus will solve it.

Alcoholics Anonymous
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Re: Design a small Sound card for Next

Post by Alcoholics Anonymous » Mon May 27, 2019 8:45 pm

PiyoTaro wrote:
Mon May 27, 2019 7:06 pm
Hmmm. I will search the literature for "/IORQULA". :shock:
I was told that this is a function after "ZX Spectrum +2".
This webpage is pretty good about documenting the various spectrum edge connectors:

https://faqwiki.zxnet.co.uk/wiki/ZX_Spe ... _connector

That page shows a common subset of signals that is portable across all models. There are links there that show the three types of spectrum edge connectors with all their signals: 48k, 128k, +3.

The next edge connector is a 48k/128k one (not a +3). The differences from the common subset page above is only +5/+9 is available, /IORQULA is available on lower 13, lower 15 and upper 4 (the +3 romcs signals) are disconnected, and upper 28 is connected but we're not sure what to do with it yet.
If there is a conflicting problem in decoding the "even" address, will the problem not occur if "A0" is not used?
To avoid conflicts with port 0xfe, you must check that A0=1.
And to avoid conflicts with ports xxFD, A1:A0 must not be "01".
In addition to the 8-bit IO decoding, A8 and A9 are used for TIMEX's AY interface that I referred to.
If A15:A8 are used in the port decoding then you must use "IN r,(C)" and "OUT (C),r" instructions to access the device as only these instructions make a full 16-bit port address that is independent of the data being OUTed. The "IN A,(n)" and "OUT (n),a" instructions place A on the upper 8-bits of the address bus but in an OUT, the upper 8-bits is not independent of the data being written.

The timex is different as it completely decodes all io ports. On a spectrum, port 0xfe is active when A0=0 but on a timex port 0xfe is only active if A7:A0=0xfe. With timex machines there is considerably more freedom in selecting port addresses.

Sinclair was a bit cheap and didn't expect anyone to have more than one or two devices plugged in. In the next we have dozens and it is a minefield to find a non-conflicting port address :)

So there are two approaches to help out. The easy one is to find a port address that doesn't conflict. Another way is to use /IORQULA when it is available to disable ports internal to the machine.

I'm a little reluctant to say how the expansion bus is being handled because we don't know if it works yet but it's directly relevant to what you are doing.

The /IORQULA signal is there but it has to be asserted very early in the io cycle before /IORQ goes low. So it must be generated by peripherals by looking at the address lines only. Right now only port 0xfe is disabled by /IORQULA being pulled high (you must only drive /IORQULA high and otherwise let it float). But I think it's likely it will be applied to at least the xxFD ports and maybe all of the internal ports. If present on original spectrums, then /IORQULA only disables port 0xfe to allow use of even port numbers.

The expansion bus is going to be off by default and must be turned on by the user. While the expansion bus is off, signals will be held in a neutral state.

When the expansion bus is on, the cpu speed will be limited to 3.5MHz (but maybe settable in the future). The user can disable internal devices individually. If the next determines that a port is being answered internally, it will not propagate the io cycle to the expansion bus. So external peripherals will not see an io cycle handled by an internal device.

Regarding your FM device, I don't know if you are still considering having it respond on port FFFD, BFFD as there is software out there for some FM devices on these ports. But it would be possible by setting the expansion bus register to disable the internal AY chips when the expansion bus is on. Then the internal AY chips will not respond to ports BFFD, FFFD and the io cycle will propagate to the expansion bus where your device can respond.

Anyway, it is easiest if you can find a non-conflicting port.

PiyoTaro
Posts: 181
Joined: Thu Jun 01, 2017 11:13 am

Re: Design a small Sound card for Next

Post by PiyoTaro » Tue May 28, 2019 7:25 pm

  • 2019/6/2
    There was a problem solution.
PiyoTaro wrote:
Thu May 23, 2019 5:31 pm
PiyoTaro wrote:
Thu May 23, 2019 5:22 pm
PiyoTaro wrote:
Tue Apr 30, 2019 1:52 pm
PCB board module does not work
PiyoTaro wrote:
Mon May 27, 2019 7:06 pm
Hmmm. I will search the literature for "/IORQULA". :shock:
---
Solution:
If there is a conflicting problem in decoding the "even" address, will the problem not occur if "A0" is not used?

I will try prototyping using "A9" instead of "A0".

Today's (tonight) work:
(Photo May.29: Since the pinsocket and IC socket were mounted on the printed circuit board, I cut the printed pattern and wired the yellow vinyl wire)
20190529_patchwork_mypcb_bottom.jpg
20190529_patchwork_mypcb_bottom.jpg (159.78 KiB) Viewed 677 times
Replace the print pattern “A0” signal with “A8”.
Replace the signal "A8" to the soundchip Pin18'A1' with "A9"
Replacement of HC138 output. Replace "Y6" with "Y4". (Always A1='0', A2='1', only A8 changes)
2019/6/16 Added.
Incorrect "patchwork" treatment.
I added a jumper to change "A0" connected to the sound chip A0 to "A8", but I also changed "A0" connected to "HC138".
Since "HC138" has changed the function of "determine either '$F5' or '$F6'" to "decode '$F7'", the input signal is not changed and A0 should be left as it is.
Use only the output of "HC138" for "Y7" and pull up one of the inputs of IC1D (HC08).
  • Changed the address decoding

    8bit-I/O: %1111010X= '$F5'(also '$F4')
    16bit-I/O: bit8= YM3438 'A0' bit9= YM3438 'A1'

    '$FCF5' '$00F5' YM3438 BANK'0' ADRESS
    '$FDF5' '$01F5' YM3438 BANK'0' DATA
    '$FEF5' '$02F5' YM3438 BANK'1' ADRESS
    '$FFF5' '$03F5' YM3438 BANK'1' DATA
    (2019/5/29 Correction: Change the 16bit-IO address by setting unused bit to "1".)
(I will think about the conflict issue with '$FE' later.)
  • 2019/6/1 Correction:
    The official wiki item "BOARD FEATURE CONTROL" has been updated at the end of May 2019, and an article "A note on partial decoding" has been added.

    When I posted this article, I saw the description of "Traditionally all" unused "bits are set to 1 to avoid conflicts with other devices," and came up with an address such as '$ FFF5' etc. But my mistake.(and I made that part "Italic")

    After reviewing it as a table again, my sound card may be in competition with "KempstonMouse". Some peripherals can be disabled with the "control register", so I try disabling the internal device in software.
  • Supplement 2019/6/2

    Address decoding problem. The output of HC138 was changed, and the operation was confirmed with the 8-bit I/O address '$ F7'.
    2019/6/16 Added. Incorrect "patchwork" treatment. I added a jumper to change "A0" connected to the sound chip A0 to "A8", but I also changed "A0" connected to "HC138". Since "HC138" has changed the function of "determine either '$F5' or '$F6'" to "decode '$F7'", the input signal is not changed and A0 should be left as it is.
    Replace the above address '$F5' as '$xxF7'.

    Also, when emphasizing the bank structure of the OPN2 register map, I did not notice any mistakes in the test program. General control registers exist in 'BANK0', and the register of BANK1 is used to define the instrument on ch4-6.

    ---
    The remaining work is "to lower the amplification gain of the Amplifier" first (adjust the volume difference with AY. Reduce the noise picked up from the power supply) and the module is still stored in the 'Speecy' case. I have not tested it yet.
Last edited by PiyoTaro on Sun Jun 16, 2019 9:16 am, edited 4 times in total.

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