TBBlue I/O port system

The TBBlue uses two I/O ports on the register/data system, to send and read information about hardware and settings.

Port 0x243B (9275) is write-only and is used to set the registry number, listed below.

Port 0x253B (9531) is used to access the registry value, the registry being either only a few bits or all bits only read, write or read/write, depending on the registry number set.

Some registers are accessible only during the initialization process (IPL and modules).

Registers:
(R) 0x00 (00) => Machine ID

(R) 0x01 (01) => Version (Nibble most significant = Major, Nibble less significant = Minor)

(R/W) 0x02 (02) => Reset:
  bits 7-3 = Reserved, must be 0
  bit 2 = (R) Power-on reset (PoR)
  bit 1 = (R/W) Reading 1 indicates a Hard-reset. If written 1 causes a Hard Reset.
  bit 0 = (R/W) Reading 1 indicates a Soft-reset. If written 1 causes a Soft Reset.

(W) 0x03 (03) => Set machine type, only in IPL or config mode:
   A write in this register disables the IPL 
   (0x0000-0x3FFF are mapped to the RAM instead of the internal ROM)
   bit 7 = lock timing
   bits 6-4 = Timing:
      000 or 001 = ZX 48K
      010 = ZX 128K
      011 = ZX +2/+3e
      100 = Pentagon 128K
   bit 3 = Reserved, must be 0
   bits 2-0 = Machine type:
      000 = Config mode
      001 = ZX 48K
      010 = ZX 128K
      011 = ZX +2/+3e
      100 = Pentagon 128K

(W) 0x04 (04) => Set page RAM, only in config mode (no IPL):
  bits 7-6 = Reserved, must be 0
  bits 5-0 = RAM page mapped in 0x0000-0x3FFF (64 pages of 16K = 1024K, Reset to 0 after a PoR or Hard-reset)

(R/W) 0x05 (05) => Peripheral 1 setting:
  bits 7-6 = joystick 1 mode (00 = Sinclair, 01 = Kempston, 10 = Cursor)(Reset to 0 after a PoR or Hard-reset)
  bits 5-4 = joystick 2 mode (same as joy1)(Reset to 0 after a PoR or Hard-reset)
  bit 3 = Reserved, must be 0
  bit 2 = 50/60 Hz mode (0 = 50Hz, 1 = 60Hz)(Reset to 0 after a PoR or Hard-reset)
  bit 1 = Enable Scanlines (1 = enabled)(Reset to 0 after a PoR or Hard-reset)
  bit 0 = Enable Scandoubler (1 = enabled)(Reset to 1 after a PoR or Hard-reset)

(R/W) 0x06 (06) => Peripheral 2 setting:
  bit 7 = Enable turbo mode (0 = disabled, 1 = enabled)(Reset to 0 after a PoR or Hard-reset)
  bit 6 = DAC chip mode (0 = I2S, 1 = JAP) (Only in VTrucco board)(Reset to 0 after a PoR or Hard-reset)
  bit 5 = Enable Lightpen (1 = enabled)(Reset to 0 after a PoR or Hard-reset)
  bit 4 = Enable DivMMC (1 = enabled)(Reset to 0 after a PoR or Hard-reset)
  bit 3 = Enable Multiface (1 = enabled)(Reset to 0 after a PoR or Hard-reset)
  bit 2 = PS/2 mode (0 = keyboard, 1 = mouse)(Reset to 0 after a PoR or Hard-reset)
  bits 1-0 = Audio chip mode (0- = disabled, 10 = YM, 11 = AY)

(R/W) 0x07 (07) => Turbo mode:
  bit 1-0 = Turbo (00 = 3.5MHz, 01 = 7MHz, 10 = 14MHz, 11 = 28MHz)(Reset to 00 after a PoR or Hard-reset)

(R/W) 0x08 (08) => Peripheral 3 setting:
  bits 7-6 = Reserved, must be 0
  bit 5 = Stereo mode (0 = ABC, 1 = ACB)(Reset to 0 after a PoR or Hard-reset)
  bit 4 = Enable internal speaker (1 = enabled)(Reset to 1 afeter a PoR or Hard-reset)
  bit 3 = Enable Specdrum/Covox (1 = enabled)(Reset to 0 after a PoR or Hard-reset)
  bit 2 = Enable Timex modes (1 = enabled)(Reset to 0 after a PoR or Hard-reset)
  bit 1 = Enable TurboSound (1 = enabled)(Reset to 0 after a PoR or Hard-reset)
  bit 0 = Reserved, must be 0

(R/W) 0x0A (10) => Anti-brick system (only in ZX Next Board):
  bit 7 = (W) If 1 start normal core
  bits 6-2 = Reserved, must be 0
  bit 1 = (R) Button DivMMC (1=pressed)
  bit 0 = (R) Button Multiface (1=pressed)

(R/W) 0x12 (18) => Layer 2 RAM page
 bits 7-6 = Reserved, must be 0
 bits 5-0 = SRAM page

(R/W) 0x13 (19) => Layer 2 RAM shadow page
 bits 7-6 = Reserved, must be 0
 bits 5-0 = SRAM page

(R/W) 0x14 (20) => Global transparency color
  bits 7-0 = Transparency color value (Reset to 0xE3, after a reset)

(R/W) 0x15 (21) => Sprite and Layers system
  bit 7 - LoRes mode, 128 x 96 x 256 colours (1 = enabled)
  bits 6-5 = Reserved, must be 0
  bits 4-2 = set layers priorities:
  Reset default is 000, sprites over the Layer 2, over the ULA graphics
  000 - S L U
  001 - L S U
  010 - S U L
  011 - L U S
  100 - U S L
  101 - U L S
  bit 1 = Over border (1 = yes)(Back to 0 after a reset)
  bit 0 = Sprites visible (1 = visible)(Back to 0 after a reset)

(R/W) 0x16 (22) => Layer2 Offset X
  bits 7-0 = X Offset (0-255)(Reset to 0 after a reset)

(R/W) 0x17 (23) => Layer2 Offset Y
  bits 7-0 = Y Offset (0-255)(Reset to 0 after a reset)

(R) 0x1E (30) => Active video line (MSB)
  bits 7-1 = Reserved, always 0
  bit 0 = Active line MSB (Reset to 0 after a reset)

(R) 0x1F (31) = Active video line (LSB)
  bits 7-0 = Active line LSB (0-255)(Reset to 0 after a reset)

(R/W) 0x22 (34) => Line Interrupt control
  bit 7 = (R) INT flag, 1=During INT (even if the processor has interrupt disabled)
  bits 6-3 = Reserved, must be 0
  bit 2 = If 1 disables original ULA interrupt (Reset to 0 after a reset)
  bit 1 = If 1 enables Line Interrupt (Reset to 0 after a reset)
  bit 0 = MSB of Line Interrupt line value (Reset to 0 after a reset)

(R/W) 0x23 (35) => Line Interrupt value LSB
  bits 7-0 = Line Interrupt line value LSB (0-255)(Reset to 0 after a reset)

(W) 0x28 (40) => High address of Keymap
  bits 7-1 = Reserved, must be 0
  bit 0 = MSB adress

(W) 0x29 (41) => Low address of Keymap
  bits 7-0 = LSB adress

(W) 0x2A (42) => High data to Keymap
  bits 7-1 = Reserved, must be 0
  bit 0 = MSB data

(W) 0x2B (43) => Low data to Keymap (writing this register the address is auto-incremented)
  bits 7-0 = LSB data

(R/W) 0x32 (50) => LoRes Offset X
  bits 7-0 = X Offset (0-255)(Reset to 0 after a reset)
  Being only 128 pixels, this allows the display to scroll in "half-pixels", 
  at the same resolution and smoothness as Layer 2.

(R/W) 0x33 (51) => LoRes Offset Y
  bits 7-0 = Y Offset (0-191)(Reset to 0 after a reset)
  Being only 96 pixels, this allows the display to scroll in "half-pixels",
  at the same resolution and smoothness as Layer 2.

(W) 0x40 (64) => Palette Index
  bit 7 = Remove flash (1 = disable the FLASH function, to use 32 colours) 
  bit 6-5 = Reserved, must be 0
  bits 4-0 = Select the palette index to change the default colour. 

(W) 0x41 (65) => Palette Value
  bits 7-0 = Colour for the palette index selected by the register 0x40. Format is RRRGGGBB
  After the write, the palette index is auto-incremented to the next index.

(W) 0xFF (255) => Debug LEDs (DE-1, DE-2 am Multicore only)