The question is, how difficult is to have two sets of DMA registers in FPGA, and how difficult it is to create this 1.5 channel dichotomy, and whether I overlooked some important detail making this whole idea invalid from start... But, if we talk about HW changes, here is another thought: wouldn't ...
If DMA is used in burst mode for audio for example.
Is it possible to interrupt DMA in order to to use DMA for byte block transfer (continuous mode) and then
continue to use DMA in burst mode for audio?
I was thinking more of the case that DMA and CPU is running in parallel.
I.e. in order not to loose any precious CPU cycle the burst mode could be used such that in almost every
CPU instruction also a DMA operation takes place.
What would be the "loss" for the CPU in that case?
I could not find this in the docs or the example program:
Let's say I transfer a block of RAM to the HW sprites port via DMA.
How do I know that the DMA has finished and is ready to be used for other tasks?
Hi, I'm currently looking into the problem to efficiently use the HW sprites from SW i.e. from Assembler. But I ran into a few problems and I would like to hear your ideas or solutions. The problem is simply put: How to deal with the sprite's position efficiently. When working with sprites the usual...