Z80 DMA Issues

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LaesQ
Posts: 4
Joined: Mon May 29, 2017 8:52 pm

Z80 DMA Issues

Postby LaesQ » Sun May 17, 2020 10:12 am

I'm finding issues with the 128K Spectrum and Z80 DMA on the Next. I'm using the latest firmware/core, etc. and using VGA (Mode 0, 50Hz) as I'm told this has the truest timing. If I try and run any of the Busysoft DMA Level (1,2 and 3) demos, they either don't work or aren't showing as they should. Also, I've tried enabling DMA mode in esxdos and that fails too. This relies upon the classic Z80 DMA to do the transfers and works fine on the MB03+ build (which also uses an FPGA implementation of the Z80 DMA chip). The Busysoft demos (when started) offer using port 11 or 107. I get different results from both, implying something is happening, but nothing shows as it should.

Am I doing something wrong or is the Next implementation of the Z80 DMA not quite complete/correct?

I downloaded the DMA demos from the following page:
https://velesoft.speccy.cz/data-gear.htm

LaesQ

Ped7g
Posts: 222
Joined: Mon Jul 16, 2018 7:11 pm

Re: Z80 DMA Issues

Postby Ped7g » Sun May 17, 2020 11:50 am

So... as this is being discussed also on the Russian forum, I did spend some time explaining and checking things.

Extra issue to consider (with SW from velesoft page) is, that some SW is simply bugged, and does work only on the UA880d DMA chip (East Germany clone of Zilog DMA). The UA chip does ignore the WR3.enable bit, while Zilog DMA and Next FPGA will start the transfer, when you set this bit to "1".

Unfortunately lot of early MB-02 SW does set this bit prematurely during DMA transfer init, as it was reported as bug only many years later, the bugged init is even in one Czech paper magazine in tutorial "how to program DMA on ZX", so the bug got quite spread around.

This is the commented DMA init sequence of dma-demo-level_1.zip from velesoft page:

($0B) = $C3 RESET
($0B) = $C7 RESET port A
($0B) = $CB RESET port B
($0B) = $7D WR0 + port A adr + length, A->B, transfer
($0B) = $21 A.adr = 0x4021
($0B) = $40
($0B) = $BE length = 0x07BE
($0B) = $07
($0B) = $14 WR1, A++, memoryA
($0B) = $10 WR2, B++, memoryB
($0B) = $C0 WR3, enable=1
DMA Transfer with mode 0 (single byte) requested - ignored
($0B) = $AD
($0B) = $20
($0B) = $40
($0B) = $82
($0B) = $CF
($0B) = $B3
($0B) = $87
...

As you can see, the demo does trip the DMA transfer before the whole init sequence is finished.

(if it works on MB-03, then I guess it ignores the WR3.enable bit too, emulating the UA chip rather then the Zilog chip. Which IMO makes sense for the MB community ... and makes me wonder if it would make sense also for global community, does anyone know, if there is SW which breaks with WR3.enable bit ignored? Like using it to enable the transfer? Because IIRC even the Zilog docs recommend the WR6 ENABLE command over the WR3 bit, so I would guess 90% of SW written for Zilog chip does not need the WR3 enable bit).

azesmbog
Posts: 4
Joined: Mon May 29, 2017 9:12 pm

Re: Z80 DMA Issues

Postby azesmbog » Thu May 21, 2020 12:28 pm

LaesQ wrote:
Sun May 17, 2020 10:12 am
Am I doing something wrong or is the Next implementation of the Z80 DMA not quite complete/correct?
LaesQ
I ran all the demos.
I can say that the implementation of zxnDMA is quite accurate, not 100% of course, but I think that 98 percent of the demonstrations show exactly what their authors intended. Of course, there are artifacts in the image, I know how it should look ideally and how it really looks.
If interested - I can provide photos from the screen.

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varmfskii
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Location: Stone Mountain, GA USA

Re: Z80 DMA Issues

Postby varmfskii » Thu May 21, 2020 8:17 pm

There are currently two ports for DMA on the ZX Next. One is supposed to emulate a traditional Zilog DMA chip (along with its peculiarities) and a second one that is not as peculiar. One should be used for compatibility, and the other is probably best for new software.
Backer #2741 - TS2068, Byte, ZX Evolution

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SevenFFF
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Joined: Mon Jun 05, 2017 5:30 pm
Location: USA

Re: Z80 DMA Issues

Postby SevenFFF » Thu May 21, 2020 8:53 pm

Previously both DMA modes were available on both ports, and the mode was switched with a nextreg bit.

Now one mode is available on each port, and the nextreg bit has been repurposed to control audio behaviour.

It’s just possible that some older software needs updating to reflect this.
Robin Verhagen-Guest
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Ped7g
Posts: 222
Joined: Mon Jul 16, 2018 7:11 pm

Re: Z80 DMA Issues

Postby Ped7g » Fri May 22, 2020 1:58 am

Robin: most of the old SW does either go to 0x0B by default or offers it as an option. So the Zilog/zxnDMA mode is usually not an issue (since core3.1.5). (BTW the port 0x0B did not exist in 3.x cores before, Allen was surprised to hear about it, but I think it did work back in core 1.x or maybe even 2.x times, but at some point it must have been removed, or it was only planned and never made it into VHDL at all)

But most of the old SW has that WR3.enable=1 bug in DMA init sequence, so it will not work correctly on Next. Only SW which did work on actual Zilog DMA chip correctly (and it does not trigger transfer prematurely) has good chance to work on Next (which is quite a minority from that velesoft web page, most of it does work only on the clone chips which ignore the WR3.enable).


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