My MiSTER Next Board - A fun experiment but ultimate failure

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dave18
Posts: 186
Joined: Tue May 30, 2017 1:06 am
Location: Bristol, UK

My MiSTER Next Board - A fun experiment but ultimate failure

Postby dave18 » Sun Mar 21, 2021 12:21 pm

I've been quietly playing around with circuit design to see if it was possible to create a board that plugged on top of the MiSTER to give a good amount of Spectrum Next features and compatibility.

I designed a board that would have:
Native Spectrum Next VGA Out (HDMI through the normal MiSTER route)
2mb SRAM using AS7C34096A-10 ICs to provide compatibility
EAR/MIC socket
Audio out
J13 header for physical SD cards (using a device like those sold by Active Consult)
2 DB9 joystick ports for lag free input
The NMI, Drive and reset buttons

While the board works, and I've successfully got a Spectrum Next core up and running I've run into memory speed issues. Everything is fine at 7hz (I'm forcing this limit though the CPU clock muxes). At 14mhz everything apart from DMA seems fine. At 28mhz it won't run and gives file access errors upon trying to load the initialisation files.

I'm assuming the amount of routing (through several vias) to fit everything on such a small board is causing signal issues (not sure if it is capacitance, track length, signal noise or all 3 of the above). It is beyond my skill level to analyse the problem and in light of a Spectrum Next core now release for MiSTER that uses SDRAM I think this project has run it's course.

I thought it was worth a post though in case anyone was interested in it or had any suggestions around how the memory speed issue might be fixed without a complete rework.

Github link below

https://github.com/dave18/SpecNext_MiSTER_Board

Cheers

Dave

Alcoholics Anonymous
Posts: 781
Joined: Mon May 29, 2017 7:00 pm

Re: My MiSTER Next Board - A fun experiment but ultimate failure

Postby Alcoholics Anonymous » Sun Mar 21, 2021 6:10 pm

I don't think the mister solution for sdram is going to work flawlessly especially as Next games start to depend on layer 2 and 28MHz speed. That solution is adding wait states at even 14MHz so it could be the 28MHz speed with layer 2 active isn't a lot faster than 14MHz. The Next does insert one wait state on every memory read cycle at 28MHz and that leads to an effective cpu speed of ~23MHz on Next hardware. I'm still waiting to see people try things out to determine how much impact there is. IF (and it's a big IF as it stands now) there is space in the fpga, the dma will be modified to soak up spare sram bandwidth and this will increase the number of channels to sram from 2 to 3. That would throw a wrench in the sdram solution.

The SRAM interface operates at 28MHz on the Next with one memory read or write confined to each cycle. You do have to make sure the track lengths are as equal as possible, as close the fpga as possible and best case no vias. We have problems with getting good builds on the native Next pcb too and it's likely due to the sram timing. The signals out to the sram may need special timing constraints added to make sure the fpga synthesis doesn't add unnecessary delays to signals.
Last edited by Alcoholics Anonymous on Sun Mar 21, 2021 6:52 pm, edited 1 time in total.

dave18
Posts: 186
Joined: Tue May 30, 2017 1:06 am
Location: Bristol, UK

Re: My MiSTER Next Board - A fun experiment but ultimate failure

Postby dave18 » Sun Mar 21, 2021 6:39 pm

Thanks for the info, sounds like it will be a challenge complying with all those constraints over a pin header. Out of interest do you know if the MiSTER version that uses the SRAM board runs at 28mhz without issue or additional (ie more than the official core) wait states?

Alcoholics Anonymous
Posts: 781
Joined: Mon May 29, 2017 7:00 pm

Re: My MiSTER Next Board - A fun experiment but ultimate failure

Postby Alcoholics Anonymous » Sun Mar 21, 2021 6:51 pm

dave18 wrote:
Sun Mar 21, 2021 6:39 pm
Thanks for the info, sounds like it will be a challenge complying with all those constraints over a pin header. Out of interest do you know if the MiSTER version that uses the SRAM board runs at 28mhz without issue or additional (ie more than the official core) wait states?
I believe it does work at 28MHz without any changes although I am not sure how much that has actually been tested. I haven't heard about any crash issues at least.


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