Well, that's kinda obvious, although good to have it confirmed. But let me repeat it, on original Z80DMA, write to any register (except ENABLE_DMA command) acts also as implicit DISABLE_DMA command. Would be nice to know, if this is also feature of ZXNDMA, or not.Alcoholics Anonymous wrote: ↑Thu Feb 07, 2019 5:12 amYou can stop the DMA by sending a DISABLE_DMA command. Then you could read the registers to find out where the DMA is so that you could restart it later.
Hm, there are already two DMA ports (MB-02 and Datagear standards), and I would expect there's precisely zero legacy SW using both at the same time.
So... thinking wild for a moment... if the FPGA implementation for ZXNDMA can use two sets of registers, each for the other port... and one port would have higher priority, so only one DMA would access bus/memory = just like now .... you have technically one-and-half channel DMA system. For continuous mode this would act the same way as single channel DMA, but with burst mode, if the audio would be done on higher priority DMA, which would be capable to interrupt memory DMA running on lower priority port, you would have "two" channel DMA, for the price of the continuous transfer taking variable amount of cycles instead of deterministic one, although it would be possible to expect quite accurately +- few cycles what the final duration will be, so this is not any major downside.
The question is, how difficult is to have two sets of DMA registers in FPGA, and how difficult it is to create this 1.5 channel dichotomy, and whether I overlooked some important detail making this whole idea invalid from start...